Leakage Reduction Technique: MTCMOS

In modern high performance integrated circuits, more than 40% of the total active mode energy can be dissipated due to the leakage currents [1]. With more transistors integrated on die, leakage currents will soon dominate the total energy consumption of high performance ICs. The sub-threshold leakage current is one of the most dominant leakage current components [1]. It is the drain to source leakage current when the transistor is off, i.e, the applied voltage Vgs is less than the threshold voltage Vt of the transistor (weak inversion mode). The subthreshold leakage current in short channel MOSFET can be expressed as follows [1]

Where Io is the drain current with Vgs =Vt. The subthreshold current depends on the transistor parameters as listed in Table 1 [2].

Parameter	Dependence
Transistor Width (W)	Directly proportional
Transistor Length (L)	Inversely proportional
Temperature (T)	Exponential increase
Transistor Threshold Voltage (Vt)	Increase by an order of magnitude with 100mV decrease
Input Voltage (Vgs)	Exponential increase

Portable battery operated devices that have long idle times are particularly affected by this leakage power loss. Existing designs must therefore be modified in a way that it curbs the draining of battery current when it is not operational.

A popular low leakage circuit technique is the Multi threshold Voltage CMOS (MTCMOS) .This technique is based on disconnecting the low threshold voltage logic gates from the power supply and/or the ground line via cut off high threshold sleep transistor is also known as “power gating”. Several MTCMOS circuit techniques have been proposed by considering many costs such as energy overhead, wake up delay, voltage, current and etc.

Multi threshold voltage CMOS (MTCMOS) reduces the leakage by inserting high threshold devices in series to low Vth circuitry [2]. In an MTCMOS circuit as shown in Figure 1, all of the logic transistors have low threshold voltages to enhance circuit speed. In order to suppress the high subthreshold leakage current characteristics of the scaled low threshold voltage transistors, high threshold voltage switches are added between the low threshold voltage logic circuits and the power supply and ground lines [3]. These high threshold voltage power supply and ground switches are controlled by a sleep signal. A sleep control scheme is introduced for efficient power management. During the active mode of operation, the sleep control switches are activated, providing a virtual power and ground line for the logic circuits. Since their ON resistances are small, the virtual power and ground line almost functions as real power line. During the standby mode, these high threshold voltage sleep control switches are turned off, reducing the subthreshold leakage current. This technique is also called power gating.

Figure 1: Schematic of MTCMOS circuit

      In fact, only one type of high Vth transistor is enough for leakage control. Figure 1(b) and (c) shows the PMOS insertion and NMOS insertion schemes respectively. The NMOS insertion scheme is preferable, since the NMOS on resistance is smaller at the same width; therefore it can be sized smaller than corresponding PMOS. The effect of an on resistance NMOS sleep transistor in series with a low Vth circuit can be approximated very accurately by replacing the high Vth device with a single linear resistor, R as shown in Figure 2. During normal circuit operation, the virtual ground node is close to real ground, so Vds of the sleep transistor is small and the resistive approximation is very accurate .

Figure 2: Sleep Transistor modelled as resistor

With the continous scaling of CMOS devices, leakage current is becoming a major contributor to the total power consumption. In current deep-submicrometer devices with low threshold voltages, subthreshold and gate leakage have become dominant sources of leakage. Power gating techniques have become very common in literature and in practice, and MTCMOS implementations in particular have demonstrated significant improvements in standby power consumption.

Written by :
Nordiana Mukahar

References:

[1] Stan, M.R.; Barcella, M., “MTCMOS with outer feedback (MTOF) flip-flops,” Proceeding of the IEEE International Symposium on Circuits and Systems, pages 429 - 432, May 2003.

[2] Kao, J.; Chandrakasan, A.; Antoniadis, D., “Transistor Sizing Issues And Tool For Multi-threshold Cmos Technology,” Proceedings of the 34^th Design Automation Conference, pages 409-414, June 1997.

[3] Volkan Kursun,; Eby G. Friedman.; “Multi-voltage CMOS Circuit Design,” pages 75-77, 2006.